1. Technical Field
The present invention generally relates to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus having a SerDes structure and a semiconductor integrated circuit including the same.
2. Related Art
Recently, with the increase in operation speed of semiconductor memory apparatuses, the number of data processed at a time by each bank has increased. Accordingly, the number of data input/output lines connected to each bank has also increased. The increase in the number of data input/output lines may serve as a factor to increase a semiconductor memory chip area.
Accordingly, a SerDes data input/output structure has been proposed to prevent an increase in area of a semiconductor memory apparatus based on the increase in the number of data input/output lines.
In a general semiconductor memory apparatus, the SerDes data input/output structure refers to a structure in which one bank has eight octet banks and any one octet bank corresponding to a first group of data and any one octet bank corresponding to a second group of the data form a pair connected to one data input/output line.
Since the semiconductor memory apparatus having the SerDes structure loads two data into one data input/output line, the number of data input/output lines may be reduced to ½.
Accordingly, the semiconductor memory apparatus having the SerDes structure receives an internal command of a data signal to be inputted to two octet banks once per two clocks, while an existing semiconductor memory apparatus receives an internal command once per four clocks. According to the internal command, a data enable signal ENDIO for loading data into a data input/output line is also generated once per two clocks.
In such a general semiconductor memory apparatus, when a memory bank receives data from a data input/output line, the data is loaded into the data input/output line once per two clocks according to a CAS internal command. However, according to a bank input enable signal BWEN as a strobe signal, the memory bank receives data once per four clocks. Therefore, the data may not be inputted to the memory bank, or data of a first octet bank may not be received, but only data of a second octet bank may be received.